International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
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<![CDATA[DESIGN AND IMPLEMENTATION OF AMBIENT NOISE CANCELLATION SYSTEM USING ADAPTIVE FILTERS AND EQUALIZATION TECHNIQUES FOR SIGNAL PROCESSING APPLICATIONS ]]>
<![CDATA[Hajare, Raju]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp%p
<![CDATA[Signal Processing is very important as it gives us the flexibility of using same hardware Processing capabilities to different applications. Aim here is to design a Noise Cancellation system that uses adaptive filter techniques to eliminate any low frequency noise from the environment, leaving the music to play from the headphones without the noise waves. In the course of achieving this, we identify the original signal and generate the inverse without delay in all directions where noises interact and superimpose. We also demonstrate the approaches that we take on tackling the noise cancellation effects, along with results comparison.]]>
<![CDATA[Dynamic modeling of the birefringence effects induced in semiconductor optical amplifier for all-optical telecommunication systems ]]>
<![CDATA[A. Elyamani]]>;
<![CDATA[A. Zatni]]>;
<![CDATA[A. Moumen]]>;
<![CDATA[H. Bousseta]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp93-101
<![CDATA[The semiconductor optical amplifiers (SOA) are all-optical multifunctional devices. The improvement of their performance will, therefore, be of great importance for modern optical telecommunication systems. We propose in this article to develop a dynamic model that enables us to simulate the dynamic behavior of SOA's birefringence effects. The determination of a numerical model is a multidisciplinary activity that needs engineering skills, optimization and physics. This numerical model enables to describe the propagation of a picosecond optical pulse passing through the SOA and takes into account its polarization and the phenomenon of energy coupling between the eigenmodes of SOA (TE mode and TM mode). In this paper, we will, first of all describe the numerical algorithm of our model, and then we will propose to make a dynamic characterization of the effect of the nonlinear polarization rotation in the SOA, which will allow us to study the all-optical logic gates as well as all the other digital components based on the nonlinear effect of birefringence in SOA.]]>
<![CDATA[IMPLEMENTED WITH DUAL MATERIAL GATE SILICON-ON- INSULATOR JUNCTIONLESS CMOS CIRCUITS ]]>
<![CDATA[Wagaj, S. C.]]>;
<![CDATA[Patil, S. C.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp%p
<![CDATA[In this research paper, we demonstrate the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). A comparison of circuit performance of the n and p channel dual material gate silicon on insulator transistor and junctionless transistor. The logic performance of a CMOS circuits is evaluated in terms of static power dissipation, output voltage v/s input voltage, propagation delay and noise margin. When metal oxide semiconductor field effect transistor (MOSFET) in saturation region gate capacitance of junctionless transistor reduces compare to with junction transistor. The circuit simulation result CMOS inverter propagation delay of junctionless transistor is reduced by 25% compare with junction transistor. DMG SOI JLT common source amplifier gives amplification of 1.25 times which is higher than DMG SOI transistor. The noise margin of junctionless CMOS inverter is 23% maximum compared to with junction CMOS inverter. NAND gate static power dissipation of DMG SOI JLT is improved by 53%, 46% and 34% compared to DMG SOI Transistor at 20nm, 30nm and 40nm channel length. On current of dual material gate junctionless transistor is increases when channel length increase compare to with junction transistor. Static power dissipation of junctionless transistor inverter is reduced by 3% compared to with junction transistor inverter at channel length 30nm.]]>
<![CDATA[Design and development of combat robot for military applications ]]>
<![CDATA[Raju Hajare]]>;
<![CDATA[Mallikarjuna Gowda C.P]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp125-132
<![CDATA[In this paper we have developed a combat robot which will assist our commandos to fight against terrorism. With additional weaponry system it can perform other tasks also. Our preliminary aim in this project is to design a combat robot which can be used to handle the unmanned situations like terror attack inside the building where the firing is heavy and the entry of commandos may be difficult. In such situations the combat robot with spy camera, which is controlled through the control room can be sent into the terrorist occupied area. The robot constantly sends the visuals captured through spy camera to the control room. Based on the visuals received from the robot the control room operator can give directions to the robot. This kind of spy robot can also be used in star hotels, shopping malls, jewelry show rooms.]]>
<![CDATA[A hardware system with ARM-based data processing for nano satellites ]]>
<![CDATA[Adrián Stacul]]>;
<![CDATA[Daniel Pastafiglia]]>;
<![CDATA[Ariel Di Giovanni]]>;
<![CDATA[Martín Morales]]>;
<![CDATA[Sergio Saluzzi]]>;
<![CDATA[Gerardo García]]>;
<![CDATA[Agustín Gadea]]>;
<![CDATA[Ramiro Puga]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp102-108
<![CDATA[The Institute of Scientific and Technical Research for Defense in Argentina (Instituto de Investigaciones Científicas y Técnicas para la Defensa - CITEDEF) is developing a processing hardware module based on a ARM Cortex M4 processor from STMicroelectronics. The microcontroller (MCU) has the capacity to run at a maximum clock frequency of 180 MHz, integrates a Floating Point Unit (FPU). An 8MB SDRAM was included for dynamic data allocation. This hardware will host and process the algorithms to calculate and determine the nanosatellite’s attitude. The module is intended to be Cubesat compatible, possess a flexible design, handles various inertial sensors and can manage backups on microSD memory cards with sizes up to 32GB.]]>
<![CDATA[Design and analysis of different full adder cells using new technologies ]]>
<![CDATA[Nandhaiahgari Dinesh Kumar]]>;
<![CDATA[Rajendra Prasad Somineni]]>;
<![CDATA[CH Raja Kumari]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp116-124
<![CDATA[CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.]]>
<![CDATA[Data ecryption based on multi-order FrFT, and FPGA implementation of DES algorithm ]]>
<![CDATA[A. Rabie]]>;
<![CDATA[Kh. El Shafie]]>;
<![CDATA[A. Hammuoda]]>;
<![CDATA[M. Rohiem]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp141-152
<![CDATA[Cryptography techniques need some algorithms for encryption of data. Most of available encryption techniques are used for textual data; a few of encryption methods are used for multimedia data; However, This Algorithms that are used for textual data may not be inefficient for multimedia, because it is size is greater than the text. Therefore, Cryptosystems need to find and develop a new encryption schemes for such data. The most popular symmetric key algorithms are Data Encryption Standard (DES). However, DES is may be not suitable for multimedia because it consumes times. Encryption and decryption of these data require different methods. In this paper a method for encryption/decryption data by using the nature of FrFT in signals analysis, based on multi-order Fractional Fourier Transform has been introduced. The security of the method used in the encryption work was taken into account to identify the different indicators to measure the security of the encryption Techniques. These indicators are: sensitivity proposed Techniques for the key, the complexity of the processes, and statistical analysis. The key is formed by combination of order of Fractional Fourier Transform. The encrypted data is obtained by the summation of different orders. Numerical simulation results are given to demonstrate this proposed method.]]>
<![CDATA[A system verilog approach for verification of memory controller ]]>
<![CDATA[Sowmya K B]]>;
<![CDATA[Gagana P]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp153-157
<![CDATA[Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.]]>
<![CDATA[Arduino controller based borewell child rescue system ]]>
<![CDATA[Melvin Paul Miki.V]]>;
<![CDATA[S. Prakash]]>;
<![CDATA[Amarnath. M.K.V]]>;
<![CDATA[K.Naveen Kumar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp133-140
<![CDATA[In this paper we have proposed a system for rescuing victims of bore well accidents. The proposed system is light in weight compared to existing methods, portable easy to handle and requires lesser manpower. The system design comprises of a four leg metal stand which supports the whole mechanical assemble the stand is of low weight therefore it is easy to transport it does not requires any heavy duty cranes. This stand has a round housing which holds the DC gear motor which controls the up and down motion of a robotic arm as the arm is connected to the motors shaft with pulley through a rope or heavy duty steel cable. The robotic arm has four mechanically operated fingers which can be opened or closed using a dc motor placed on the arm itself this motor controls the arm by tightening the cables which runs over the four finger joints just like a human arm. The two motors are controlled by an Arduino based remote control module containing buttons and toggle switch with the help of this module easy control of the system is achieved. In addition to this an ultrasonic sensor and a digital camera was also incorporated to predict the victim’s location. In order to determine the feasibility of the system a prototype was designed and fabricated. The prototype consists of all mechanical and electronics setup as discussed above but in a miniature version. The prototype has a control module which consist of LCD display, motor driver IC, Arduino microcontroller, control switches, buttons and power supply unit. This is the main electronics unit which controls and coordinates the whole systems operation. The project is intended to reduce the risk involved during the child rescues operation by analysing the simulation.]]>
<![CDATA[Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core ]]>
<![CDATA[Shing-Tai Pan]]>;
<![CDATA[Ching-Fa Chen]]>;
<![CDATA[Wen-Sin Tseng]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp109-115
<![CDATA[The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.]]>
